Dynamic memory

ABSTRACT

A dynamic memory having pairs of bit lines. A sense amplifier is connected between each pair of bit lines for detecting data from the potential difference between these bit lines. The memory further comprises first and second pair of dummy word lines. A capacitor is coupled between the first of each pair of bit lines, on the one hand, and the first pair of dummy word lines, on the other. Similarly, a capacitor is coupled between the second of each pair of bit lines, on the one hand, and the second pair of dummy word lines, on the other. A first dummy word line driver is connected to the first pair of dummy word lines, for generating a reference potential in the first of each pair of bit lines. A second dummy word line driver is connected to the second pair of dummy word lines, for generating a reference potential in the second of each pair of bit lines. The memory also has a selection circuit for selecting either the first or second dummy word line driver. During a precharging period, either dummy word line driver sets both pairs of dummy word lines at a precharging potential. During a data-reading period, the dummy word line driver selected by the selection circuit sets the dummy word lines at a high potential and a low potential, respectively, and the dummy word line driver selected by the selection circuit sets both dummy word lines at a precharging potential.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a dynamic memory comprising a pluralityof memory cells, each consisting of a selecting transistor and adata-storing capacitor.

2. Description of the Related Art

For a semiconductor memory it is most important that data be stably readfrom, and stably written into, the memory. For a dynamic memory whosememory cells each comprise one selecting transistor and one data-storingcapacitor, it is very important to maintain a reference potentialconstant, which is compared with the potential of a bit line, thereby todetect data. Unless the reference potential is stable, the read-outmargin of the memory cannot be sufficient. (Note: the greater theread-out margin, the smaller the change in the bit-line potential, fromwhich data can be detected.)

It will be explained how to generate a reference potential in a 1 MBDRAM. In the case of this memory having a great memory capacity, anextremely large number of memory cells are connected to each bit line,and the parasitic capacitance C_(B) of the bit line is naturally verygreat. On the other hand, there is the trend that the capacitance C_(S)of the data-storing capacitor of each memory cell is inverselyproportional to the memory capacity of the entire memory.

The voltage V0 detected from a memory cell storing logic "0" (i.e., theground potential) and the potential V_(BL) which the bit line connectedto this cell has before the reading of logic "0" have the followingrelationship:

    C.sub.B.V.sub.BL =(C.sub.B +C.sub.S).V0                    (1)

Therefore, V0 can be given as follows: ##EQU1##

The voltage V1 detected from a memory cell storing logic "1" (i.e., theV_(CC) potential) and the potential V_(BL) which the bit line connectedto this cell has before the reading of logic "1" have the followingrelationship:

    C.sub.B.V.sub.BL +C.sub.S.V.sub.CC =(C.sub.B +C.sub.S).V1  (3)

Therefore, V1 can be given as follows: ##EQU2##

It is desirable that the reference potential be exactly between V0 andV1, i.e., (V0+V1)/2. To generate a reference potential of this value,the circuit shown in FIG. 1 may be used in a DRAM. The DRAM has a pairof bit lines BL and BL. Memory cell MC is coupled to bit line BL. CellMC comprised of selecting transistor Q and data-storing capacitor C_(S).Transistor Q is to be driven by a signal on word line WLj. Twocapacitors C_(D) are connected at one end to bit line BL. Parasiticcapacitor C_(B) is connected to both bit lines BL and BL. One ofcapacitors C_(D) connected to bit line BL is coupled at the other end todummy word line DWL. The other capacitor C_(D) connected to bit line BLis coupled at the other end to dummy word line DWL. Latch-type senseamplifier SA is connected between bit lines BL and BL.

To read data from memory cell MC, both bit lines BL and BL areprecharged to a predetermined DC potential V_(BL) by a precharging means(not shown). While the bit lines are being precharged, both dummy wordlines DWL and DWL are connected to a V_(BL) potential source and thusare set at potential V_(BL). After bit lines BL and BL have beenprecharged to potential V_(BL), both dummy word lines are disconnectedfrom the V_(BL) potential source. Then, dummy word lines DWL and DWL areconnected to the V_(CC) potential source and the V_(SS) potentialsource, respectively. As a result of this, capacitors C_(D) are firstcharged and then discharged. Assuming that the potential of bit line BLchanges to Vref after capacitors C_(D) have been charged and discharged,the potential Vref, the capacitance C_(B) of capacitors C_(B), thecapacitances C_(D), and the potential V_(CC) have the followingrelationship: ##EQU3## As can be understood from equation (5), potentialVref is given as: ##EQU4##

If C_(D) =1/2C_(S), equation (6) can be transformed to the following:##EQU5##

As is evident from equation (7), the potential exactly half the readoutpotential of memory cell MC can be generated and used as referencepotential Vref, whatever potential bit line BL has before data is readout from memory cell MC. After reference potential Vref has beengenerated, sense amplifier SA detects the data stored in memory cell MCby comparing voltage V1 or V0 with reference voltage Vref.

FIG. 2 is a circuit diagram showing a conventional DRAM having means fora reference potential based on the principle described above. As isillustrated in this figure, the DRAM comprises pairs of bit lines BL1,BL1, . . . BLm, BLm, memory cells MC, word lines WL1, . . . WLn-1 andWLn, a pair of dummy word lines DWL0 and DWL0, and a pair of dummy wordlines DWL1 and DWL1. The DRAM further comprises transistors QE1 to QEm,transistors QP10, QP11 to QPm0, PQm1, latch-type sense amplifiers SA1 toSAm, row decoder RD, dummy word line drive circuits 10 and 20,capacitors C_(D) 01, C_(D) 21, . . . C_(D) 0m, and C_(D) 2m, andcapacitors C_(D) 11, C_(D) 31, . . . C_(D) 1m, and C_(D) 3m.

Each memory cell is comprised of a selecting transistor Q and adata-storing capacitor C_(S). Transistors QE1 to QEm are used toshort-circuit the bit line pairs in response to an equalizing signalEQL. Transistors QP10, QP11 to QPm1, and PQm1 are used to set the bitline pairs at potential V_(BL) in response to the equalizing signal EQL.Latch-type sense amplifiers SA1 to SAm are designed to detect data fromthe bit line pairs in response to a control signal φSA. Row decoder RDis used to drive word lines WL1, . . . WLn-1, and WLn. Circuit 10 isdesigned to drive dummy word lines DWL0 and DWL0, and circuit 20 todrive dummy word lines DWL1 and DWL1. Capacitors C_(D) 01, C_(D) 21, . .. C_(D) 0m, and C_(D) 2m are equivalent to one of two capacitors C_(D)shown in FIG. 1, and each is connected a bit line BL and dummy word lineDWL0 for generating a reference potential in bit line BL. CapacitorsC_(D) 11, C_(D) 31, . . . C_(D) 1m, and C_(D) 3m are equivalent to theother capacitor C_(D) shown in FIG. 1, and each is connected a bit lineBL and dummy word line DWL0 for generating a reference potential in bitline BL.

Dummy word line drive circuit 10 comprises transistor 11 forshort-circuiting dummy word lines DWL0 and DWL0 in response toequalizing signal EQL, transistors 12 and 13 for connecting lines DWL0and DWL0 to potential source V_(BL) in response to signal EQL, P-channeltransistor 14 for connecting dummy word line DWL0 to potential sourceV_(CC) in response to selection signal DSE0, and transistor 15 forconnecting dummy word line DWL0 to potential source V_(SS) in responseto signal DSE0.

As can be understood from FIG. 2, dummy word line drive circuit 20 isidentical in structure to dummy word line drive circuit 10. It isdifferent in the function of its elements. More specifically, transistor11 short-circuits dummy word lines DWL1 and DWL1 in response to signalEQL; transistors 12 and 13 connect lines DWL1 and DWL1 to potentialsource V_(BL) in response to signal EQL; P-channel transistor 14 couplesdummy word line DWL1 to potential source V_(CC) in response to selectionsignal DSE1; and transistor 15 connects dummy word line DWL1 topotential source V_(SS) in response to signal DSE1.

Selection signals DSE0 and DSE1, which are used in dummy word line drivecircuits 10 and 20, respectively, are selectively set at logic "1" levelin accordance with a row-address signal (not shown) which is identicalto the one supplied to row decoder RD. All transistors used in eitherdummy word line drive circuit, except for P-channel transistor 14, areof N-channel type.

Assuming that the memory cells connected to bit line BL of each pairhave been selected, then bit line BL and BL of the pair are defined asbit lines BL "1" and BL"1", respectively when the selected cells storelogic "1", and as bit lines BL "0" and BL"0", respectively, when thememory cells store logic "0".

Equalizing signal EQL falls from the V_(CC) level to the V_(SS) (0V) asis shown in FIG. 3. On the other hand, the potential of a word line WLj(j=1 to n) rises from the V_(SS) level to the 3/2 V_(CC) level. Alongwith the rise of the potential of word line WLj, selection signal DSE0rises from the V_(SS) level to the V_(CC) level. Hence, as is shown inFIG. 3, the potential of dummy word line DWL0 rises from the V_(BL)level to the V_(CC) level, whereas the potential of dummy word line DWL0falls from the V_(BL) level to the V_(SS) level. As a result of this, areference potential is generated in bit lines BL1 to BLm, as may beunderstood from the description of the circuit shown in FIG. 1. At thistime, dummy word lines DWL1 and DWL1 of the other pair are in a"floating" state. Here it is assumed that, of the memory cellssimultaneously selected by word line WLj, m cells store logic "0" and ncells store logic "1", where m<<n.

After data items have been read from the selected memory cells to bitlines BL1 to BLm, signal φSA enables sense amplifiers SA1 to SAm todetect data from bit lines BL1 to BLm. Hence, sense amplifiers SA1 toSAm start detecting the data. Thereafter, the potentials of bit linesBL"1" and bit lines BL"0" rise to the V_(CC) level, whereas thepotentials of bit lines BL"0" and bit lines BL"1" fall to the V_(SS)level. Since dummy word lines DWL1 and DWL1 are in the floating state,their potentials change in the same way as the potential of each bitline BL"1" and the potential of each bit line BL"0", respectively.

The electric charge Q0 accumulated in dummy word line DWL1 or DWL1before sense amplifiers SA1 to SAm start detecting data is given asfollows:

    Q0=C.sub.DWL.V.sub.BL                                      ( 8)

where C_(DWL) is the parasitic capacitance of the pair of dummy wordlines DWL1 and DWL1.

Assuming that upon lapse of Δt seconds after the sense amplifiers havestarted detecting data, the potentials of bit lines BL"0" and BL"1"change to V_(BL) +V_(L) and V_(BL) +V_(H), respectively, then theelectric charge QΔt is accumulated in dummy word line DWL1 or DWL1. Thiselectric charge QΔt is presented as follows: ##EQU6##

Since m<<n, the third term of equation (9) has a value far smaller thanthat of the second term and is negligible. Further, the electric chargeaccumulated in dummy word line DWL1 or DWL1 either before or after thestart of the data reading is retained. Therefore: ##EQU7## From equation(10), we obtained: ##EQU8##

If n=500, C_(D) =20pF, C_(DWL) =3pF, V_(H) =0.3 V, then V_(DWL) is 230mV. Hence, the potential of each bit line BL"0", through which logic "0"is read form the memory cells storing logic "0", rises and stays at ahigh level for some time, as is illustrated in FIG. 3. Immediately afterthe start of the data reading, the potential difference between the bitlines of any pair is small, and the data detected and latched by thesense amplifier connected to these bit lines is likely to be inverted bynoise. A rise of the potential of bit line BL"0" reduces the potentialdifference between bit lines BL"0" and BL"0", inevitably increasing thepossibility that the data detected and latched by the sense amplifier isinverted. In the worst case, the potential of bit line BL"0" rises abovethat of bit line BL"0" immediately after the start of the data reading,whereby the sense amplifier makes an error, thus reducing thereliability of the data-reading.

The data detected and latched by the sense amplifier may be invertedwhen m>>n, that is, when more memory cells store logic "0" than thosestoring logic "1", as will be understood from FIG. 4 which shows how thepotentials of the various lines change with time when m>>n. Since dummyword lines DWL1 and DWL1 are in the floating state when logic "1" areread from n memory cells through bit lines BL"1" and BL"1", thepotentials of lines DWL1 and DWL1 in the same way as those of bit linesBL"1" and BL"1", respectively. Also in this case, the potentialdifference between the bit lines of any pair is small immediately afterthe start of the data reading. In the worst case, the potential of bitline BL"1" falls below that of bit line BL"1" immediately after thestart of the data reading, whereby the sense amplifier make an error,thus reducing the reliability of the data-reading.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a reliable dynamicmemory wherein sense amplifiers correctly detect data during the initialphase of data reading.

According to the present invention, there is provided a dynamic memorycomprising a plurality of pairs of bit lines, a plurality of memorycells connected to the pairs of bit lines, a plurality of word lines forselecting the memory cells, a precharging-potential source forprecharging the bit lines, a high-potential source, and a low-potentialsource. The bit lines are precharged by means of theprecharging-potential source to read data from the memory cells. Thedynamic memory further comprises a plurality of sense amplifiers, firstand second pair of dummy word lines, a plurality of first capacitors, aplurality of second capacitors, a first dummy word drive circuit, asecond dummy word drive circuit, and a selection circuit. Each senseamplifier is coupled between a pair of bit lines for detecting data fromthe potential difference between the bit lines. Each first capacitor isconnected to the first pair of dummy word lines and also to the first ofa pair of bit lines, for generating a first reference potential. Eachsecond capacitor is connected to the second pair of dummy word lines andalso to the second of the pair of bit lines, for generating a referencepotential. The first dummy word line drive circuit is connected to thefirst pair of dummy word lines, for generating a third referencepotential in the first of each pair of bit lines. The second dummy wordline drive circuit is connected to the second pair of dummy word lines,for generating the a fourth reference potential in the second of eachpair of bit lines. The selection circuit is designed to select eitherthe first dummy word line drive circuit or the second dummy word linedrive circuit.

While the bit lines are being precharged, the first dummy word linedrive circuit sets the first pair of dummy word lines at the potentialof the precharging-potential source, and the second dummy word linedrive circuit sets the second pair of dummy word lines at the potentialof the precharging-potential source. While the data is being read frommemory cells, the dummy word line drive circuit selected by theselection circuit sets one of the pairs of dummy word lines at thepotential of the high-potential source, and the dummy word line drivecircuit not selected by the selection circuit sets the other pair ofdummy word lines at the potential of the low-potential source.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram showing the circuit used in a conventional dynamicmemory, for generating a reference potential;

FIG. 2 is a circuit diagram showing a conventional dynamic memory;

FIG. 3 is a diagram showing how the potentials of the various lines usedin the conventional dynamic memory change with time when more memorycells store logic "1" than logic "0";

FIG. 4 is a diagram showing how the potentials of the various lines usedin the conventional dynamic memory change with time when more memorycells store logic "0" than logic "1";

FIG. 5 is a circuit diagram showing a dynamic memory according to thepresent invention;

FIG. 6 is a diagram showing how the potentials of the various lines usedin the dynamic memory shown in FIG. 5 change with time; and

FIG. 7 is a circuit diagram illustrating another dynamic memoryaccording to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

A dynamic memory according to the invention will now be described, withreference to FIG. 5.

As is shown in FIG. 5, the dynamic memory comprises pairs of bit linesBL1, BL1, . . . BLm, BLm, memory cells MC, word lines WL1, . . . WLn-1and WLn, a pair of dummy word lines DWL0 and DWL0, and a pair of dummyword lines DWL1 and DWL1. The DRAM further comprises transistors QE1 toQEm, transistors QP10, QP11 to QPm0, QPm1, latch-type sense amplifiersSA1 to SAm, row decoder RD, dummy word line drivers 30 and 40,capacitors C_(D) 01, C_(D) 21, . . . C_(D) 0m, and C_(D) 2m, andcapacitors C_(D) 11, C_(D) 31, . . . C_(D) 1m, and C_(D) 3m.

Each memory cell each is comprised of a selecting transistor and adata-storing capacitor. Transistors QE1 to QEm are used to short-circuitthe bit line pairs in response to an equalizing signal EQL. TransistorsQP10, QP11 to QPm0, and QPm1 are used to set the bit line pairs atpotential V_(BL) in response to the equalizing signal EQL. Latch-typesense amplifiers SA1 to SAm are designed to detect data from the bitline pairs in response to a control signal φSA. Row decoder RD is usedto drive word lines WL1, . . . WLn-1, and WLn. Circuit 30 is designed todrive dummy word lines DWL0 and DWL0, and circuit 40 to drive dummy wordlines DWL1 and DWL1. Capacitors C_(D) 01, C_(D) 21, . . . C_(D) 0m, andC_(D) 2m are equivalent to one of two capacitors C_(D) shown in FIG. 1,and each is connected a bit line BL and dummy word line DWL0 forgenerating a reference potential in bit line BL. Capacitors C_(D) 11,C_(D) 31, . . . C_(D) 1m, and C_(D) 3m are equivalent to the othercapacitor C_(D) shown in FIG. 1, and each is connected a bit line BL anddummy word line DWL1 for generating a reference potential in bit lineBL.

Dummy word line driver 30, which is connected to dummy word lines DWL0and DWL0, sets these dummy word lines at a potential in response to theequalizing signal EQL and selection signal DSE0. Dummy word line driver40, which is connected to dummy word lines DWL1 and DWL1, sets thesedummy word lines at a potential in response to the equalizing signal EQLand selection signal DSE1.

Dummy word line driver 30 comprises MOS transistor 11 connected betweendummy word lines DWL0 and DWL0, MOS transistor 12 coupled between dummyword line DWL0 and a V_(BL) power source, MOS transistor 13 coupledbetween dummy word line DWL0 and a V_(BL) power source, P-channel MOStransistor 14 connected between a V_(CC) potential source and dummy wordline DWL0, MOS transistor 15 connected between V_(SS) (ground) potentialsource and dummy word line DWL0, inverter 16 connected to receiveselection signal DSE0, two-input NAND gate 17 and inverter 18 connectedto receive equalizing signal EQL.

In dummy word line driver 30, inverter 16 inverts selection signal DSE0supplied to it. The output signal of inverter 16 is supplied to the gateof P-channel MOS transistor 14. Selection signal DSE0 is also suppliedof the gate of MOS transistor 15 and to the first input of NAND gate 17.Equalizing signal EQL is input to inverter 18, the output of which issupplied to the second input of NAND gate 17. The output of NAND gate 17is supplied to the gates of MOS transistors 11, 12, and 13.

Dummy word line driver 40 is identical to dummy word line driver 30 instructure, as can be understood from FIG. 5. Circuit 40 is alsoidentical to circuit 30 in operation, except that selection signal DSE1,not DSE0, is supplied to inverter 16 and MOS transistor 15.

The dynamic memory has decoder 50 for generating selection signals DSE0and DSE1 which are to be supplied to dummy word line drivers 30 and 40,respectively. Decoder 50 sets either signal DSE0 or signal DSE1 at logic"1" level in accordance with the same row-address signal as is suppliedto row decoder RD.

All transistors used in either dummy word line driver, except forP-channel MOS transistor 14, are of N-channel type. Potential V_(BL) canbe obtained from the V_(CC) source in, for example, an intermediatepotential-generating circuit (not shown).

The operation of the dynamic memory described above will now beexplained with reference to FIG. 6 which shows how the potentials of thevarious lines used in the memory change with time.

In the precharging period, equalizing signal EQL is set at the logic "1"level, or the V_(CC) level. Hence, MOS transistors QE and QP connectedto bit lines BLi and BLi of each pair, respectively, are turned on, thusprecharging bit lines BLi and BLi to the V_(BL) potential, that is,setting these bit lines at the same potential. Both selection signalsDSE0 and DSE1 are at the logic "0" level at this time, and MOStransistors 14 and 15 incorporated in each dummy word line driver areoff. Since signal EQL has been set at the logic "1" level, the output ofinverter 18 used in each dummy word line driver is at the logic "0"level, whereby NAND gate 17 outputs a signal at the logic "1" level. Asa result, MOS transistors 11, 12, and 13 provided in each dummy wordline driver are turned on, and dummy word lines DWL0, DWL0, DWL1, andDWL1 are set to the V_(BL) potential.

In the data-reading period, equalizing signal EQL, which has been at thelogic "1" level during the precharging period, is set at the logic "0"level. As a result of this, MOS transistors QE and QP coupled to bitlines BL and BL of each pair, respectively, are turned off, thusdisconnecting each pair of bit lines from the V_(BL) potential source.Since signal EQL has been set to the logic "0" level, the output ofinverter 18 provided in each dummy word line driver is set to the logic"1" level. Nonetheless, MOS transistors 11, 12, and 13 incorporated ineach dummy word line driver remain on since both selection signals DSE0and DSE1 are still at the logic "0" level. Therefore, dummy word linesDWL0, DWL0, DWL1, and DWL1 remain at the V_(BL) potential.

Thereafter, the row-address signal is changed. In accordance with therow-address signal, decoder 50 sets either signal DSE0 or signal DSE1 atthe logic "1" level. Assuming that signal DSE0 is set at the logic "1"level, MOS transistors 14 and 15 used in dummy word line driver 30 areturned on. In driver 30, the output of inverter 18 of driver 30 is atthe logic "1" level, and the output of NAND gate 17 therefore falls tothe logic "0" level. Hence, MOS transistors 11, 12, and 13, which areused in driver 30, are turned off. Dummy word line DWL0 is charged byMOS transistor 14, from the V_(BL) potential to the V_(CC) potential;dummy word line DWL0 is discharged by MOS transistor 15, from the V_(BL)potential to the V_(SS) potential. As a result of this, such a referencepotential Vref as has been described is generated in bit line BL of anypair. The charging of line DWL0 and the discharging of line DWL0 areachieved by means of capacitors C_(D) 01, C_(D) 21, . . . C_(D) 0m, andC_(D) 2m.

Assuming that row decoder RD selects one word line, for example, wordline WL2, in accordance with the row address signal, the potential ofword line WL2 rises from the V_(SS) level to the 3/2 V_(CC) level.Hence, data is read from the memory cells connected to this word lineWL2 and bit lines BL of all pairs. More precisely, the potentialrepresenting the data is generated in these bit lines BL, and thereference potential Vref is generated in the bit lines BL forming pairsjointly with the bit lines BL.

Thereafter, when control signal φSA rises to the logic "1" level, senseamplifiers SA1 to SAm are enabled to detect data. Dummy word lines DWL1and DWL1 coupled by capacitors C_(D) 11, C_(D) 31, . . . C_(D) 1m, andC_(D) 3m to bit lines BL, which are connected to the selected memorycells, remain at the V_(BL) -level potential. Signal DSE1 thereforeremains at the logic "0" level. Hence, in dummy word line driver 40, theoutput of NAND gate 17 remains at the logic "1" level even if equalizingsignal EQL falls to the logic "0" level, thus raising the output ofinverter 18 to the logic "1" level. MOS transistors 11, 12, and 13incorporated in driver 40 remain on, and dummy word lines DWL1 and DWL1stay at the V_(BL) -level potential. Neither line DWL1 nor line DWL1 isin the floating state as in the conventional dynamic memory (FIG. 2).The potential of all bit lines BL, to which the selected memory cellsare connected, is not adversely influenced by the potentials of dummyword lines DWL1 and DWL1. As a result, sense amplifiers SA1 to SAm candetect the data with sufficient accuracy. Hence, the dynamic memory isgreatly reliable.

Decoder 50 is designed, by means of a specific combination of logicelements, to set selection signal DSE1 at the logic "1", therebyselecting dummy word line driver 40, when the row-address signal changesin such a way that row decoder RD drives the odd-numbered word linesWL1, WL3, . . . WLn. Decoder 50 is also designed and to set selectionsignal DSE0 at the logic "1", thereby selecting dummy word line driver30, when the row-address signal changes in such a way that row decoderRD drives the even-numbered word lines WL2, WL4, . . . WLn-1.

FIG. 7 shows another dynamic memory according to the present invention,This memory is different from the memory described above, in that dummyword line drivers 60 and 70 are used in place of drivers 30 and 40, bothshown in FIG. 5. Each dummy word line driver differs from itscounterpart shown in FIG. 5, in that two N-channel MOS transistors 19and 20 replace inverter 18 and NAND gate 17.

In dummy word line driver 60, N-channel MOS transistor 19 is connectedbetween dummy word line DWL0 and a V_(BL) potential source, N-channelMOS transistor 20 is coupled between dummy word line DWL0 and the V_(BL)potential source, and the output of inverter 16 is supplied to the gateof both N-channel MOS transistors 19 and 20. Similarly, in dummy wordline driver 70, N-channel MOS transistor 19 is connected between dummyword line DWL1 and the V_(BL) potential source, N-channel MOS transistor20 is coupled between dummy word line DWL1 and the V_(BL) potentialsource, and the output of inverter 16 is supplied to the gate of bothN-channel MOS transistors 19 and 20.

In operation, when equalizing signal EQL falls from the logic "1" levelto the logic "0" level, transistors 11, 12, and 13 used in each dummyword line driver are turned off. When both selection signals DSE0 andDSE1 are at the logic "0" level, the output of inverter 16 of each dummyword line driver is at the logic "1" level. Thus, MOS transistors 19 and20 of each dummy word line driver remain on, and dummy word lies DWL0,DWL0, DWL1, and DWL1 are set at the V_(BL) potential. Assuming thatselection signal DSE0 rises from the logic "0" level to the logic "1" inthis condition, MOS transistors 14 and 15 provided in driver 60 areturned on. Dummy word line DWL0 is therefore charged by transistor 14 ofdriver 60 from the V_(BL) potential to the V_(CC) potential, whereasdummy word line DWL0 is discharged by

transistor 15 from the V_(BL) potential to the V_(SS) potential. Sinceselection signal DSE1 remains at the logic "0" level, MOS transistors 19and 20 used in driver 70 are still on, and the potentials of dummy wordlines DWL1 and DWL1 remain at the V_(BL) level.

The present invention has been described with reference to theembodiments. Nonetheless, the invention is not limited to theseembodiments. Various changes and modifications can be made withoutdeparting from the scope of the invention. For instance, this inventioncan also apply not only to CMOS dynamic memories (the aboveembodiments), each comprising P-channel MOS transistors and N-channelMOS transistors, but also to a dynamic memory comprising eitherP-channel MOS transistors or N-channel MOS transistors. The V_(BL)potential source for precharging the bit lines is not limited to anintermediate potential-generating circuit, and can be an external powersource.

What is claimed is:
 1. A dynamic memory comprising:pairs of bit lines; aplurality of memory cells connected to each pair of bit lines; aplurality of word lines for selecting the memory cells; a prechargingpotential source for precharging said pairs of bit lines during aprecharging period which precedes a data-reading period; ahigh-potential source; and a low-potential source; a plurality of senseamplifiers, each connected between a pair of bit lines, for detectingdata during the data-reading period from a potential difference betweenthe pair of bit lines; a first pair of dummy word lines; a second pairof dummy word lines; first capacitors, each connected between said firstpair of dummy word lines, on the one hand, and the first of thecorresponding pair of bit lines, on the other hand, for generating areference potential; second capacitors, each connected between saidsecond pair of dummy word lines, on the one hand, and the second of thecorresponding pair of bit lines, on the other hand, for generating areference potential; a first dummy word line driving circuit connectedto said first pair of dummy word lines, for generating the referencepotential in the first of each pair of bit lines; a second dummy wordline driving circuit connected to said second pair of dummy word lines,for generating the reference potential in the second of each pair of bitlines; and a selection circuit for selecting either said first dummyword line driving circuit or said second dummy word line drivingcircuit, wherein during said precharging period, said first and seconddummy word line driving circuits set said first and second pairs ofdummy word lines at the potential of said precharging potential source,and during said data-reading period, the dummy word line driving circuitselected by said selection circuit sets the pair of dummy word lines atthe potential of said high-potential source and the potential of saidlow-potential source, respectively, and the dummy word line drivingcircuit not selected by said selection circuit sets the pair of dummyword lines at the potential of said precharging potential source.
 2. Thedynamic memory according to claim 1, wherein said first capacitors andsaid second capacitors have the same capacitance.
 3. The dynamic memoryaccording to claim 1, wherein said selection circuit selects either saidfirst dummy word line driving circuit or said second dummy word linedriving circuit, in accordance with an address signal for driving saidword lines.
 4. The dynamic memory according to claim 1, wherein each ofsaid dummy word line driving circuits comprises:first and secondswitching means connected between said pair of dummy word lines and saidprecharging potential source; third switching means connected betweenthe first of said pair of dummy word lines and said high-potentialsource, said third switching means being turned on during saiddata-reading period; fourth switching means connected between the secondof said pair of dummy word lines and said low-potential source, saidfourth switching means being turned on during said data-reading periodwhen selected by said selection circuit; and control means connected toreceive a precharge control signal and an output signal of saidselection circuit, for turning on said third and fourth switching meansduring said precharging period, and for turning on said first and secondswitching means during said data-reading period when selected by saidselection circuit.
 5. The dynamic memory according to claim 4, whereinsaid first to fourth switching means are MOS transistors.
 6. The dynamicmemory according to claim 4, wherein said control means comprises a gatecircuit connected to receive said precharge control signal and theoutput of said selection circuit.
 7. The dynamic memory according toclaim 4, wherein each of said dummy word line driving circuitscomprises:first and second switching means connected between said pairof dummy word lines and said precharging potential source; thirdswitching means connected between the first of said pair of dummy wordlines and said high-potential source, said third switching means beingcontrolled by an output signal of said selection circuit; fourthswitching means connected between the second of said pair of dummy wordlines and said low-potential source, said fourth switching means beingcontrolled by the output of said selection circuit; fifth switchingmeans connected between the first of said pair of dummy word lines andsaid precharging potential source, said fifth switching means beingcontrolled by an output signal of said selection circuit; and sixthswitching means connected between the second of said pair of dummy wordlines and said precharging potential source, said sixth switching meansbeing controlled by the output of said selection circuit.
 8. The dynamicmemory according to claim 7, wherein said first to sixth switching meansare MOS transistors.
 9. The dynamic memory according to claim 4, whereineach of said first and second dummy word line driving circuits furthercomprises switching means connected between the pair of dummy wordlines, for supplying an equalizing signal under the control of saidprecharge control signal.
 10. The dynamic memory according to claim 7,wherein each of said first and second dummy word line driving circuitsfurther comprises switching means connected between the pair of dummyword lines, for supplying an equalizing signal under the control of saidprecharge control signal.
 11. The dynamic memory according to claim 1,further comprising a plurality of switching means, each connectedbetween the pair of bit lines, for supplying an equalizing signal underthe control of said precharge control signal.
 12. A dynamic memorycomprising:pairs of bit lines; a plurality of memory cells connected toeach pair of bit lines; a plurality of word lines for selecting thememory cells; a precharging potential source for precharging said pairsof bit lines during a precharging period which precedes a data-readingperiod; a high-potential source; and a low-potential source; a pluralityof sense amplifiers, each connected between a pair of bit lines, fordetecting data during the data-reading period from a potentialdifference between the pair of bit lines; a first pair of dummy wordlines; a second pair of dummy word lines; first capacitors, eachconnected between said first pair of dummy word lines, on the one hand,and the first of the corresponding pair of bit lines, on the other hand,for generating a reference potential; second capacitors, each connectedbetween said second pair of dummy word lines, on the one hand, and thesecond of the corresponding pair of bit lines, on the other hand, forgenerating a reference potential; a first dummy word line drivingcircuit connected to said first pair of dummy word lines, for generatingthe reference potential in the first of each pair of bit lines; a seconddummy word line driving circuit connected to said second pair of dummyword lines, for generating the reference potential in the second of eachpair of bit lines; and a selection circuit for selecting either saidfirst dummy word line driving circuit or said second dummy word linedriving circuit, wherein each of said dummy word line driving circuitscomprises: first MOS transistor connected between the first of the pairof dummy word lines and said precharging potential source; second MOStransistor connected between the second of the pair of dummy word linesand said precharging potential source; third MOS transistor connectedbetween the first of the pair of dummy word lines and saidhigh-potential source, said third MOS transistor being turned on duringsaid data-reading period when selected by said selection circuit; fourthMOS transistor connected between the second of said pair of dummy wordlines and said low-potential source, said fourth MOS transistor beingturned on during said data-reading period when selected by saidselection circuit; and a gate circuit connected to receive a prechargecontrol signal and an output signal of said selection circuit, forturning on said first and second MOS transistors during said prechargingperiod, and for turning on said third and fourth MOS transistors duringsaid data-reading period when said selection circuit outputs no signals.13. The dynamic memory according to claim 12, wherein said firstcapacitors and said second capacitors have the same capacitance.
 14. Thedynamic memory according to claim 12, wherein said selection circuitselects either said first dummy word line driving circuit or said seconddummy word line driving circuit, in accordance with an address signalfor driving said word lines.
 15. A dynamic memory comprising:a pluralityof pairs of bit lines; a plurality of memory cells connected to eachpair of bit lines; a plurality of word lines for selecting the memorycells; a plurality of potential source for precharging said pairs of bitlines during a precharging period which precedes a data-reading period;a high-potential source; a low-potential source; a plurality of senseamplifiers, each connected between a pair of bit lines, for detectingdata during the data-reading period from a potential difference betweenthe pair of bit lines; a first pair of dummy word lines; a second pairof dummy word lines; first capacitors, each connected between said firstpair of dummy word lines and the first pair of the corresponding pair ofbit lines, for generating a reference potential; second capacitors, eachconnected between said first second pair of dummy word lines and thesecond of the corresponding pair of bit lines, for generating areference potential; a first dummy word line driving circuit connectedto said first pair of dummy word lines for generating the referencepotential in the first of each pair of bit lines; a second dummy wordline driving circuit connected to said second pair of dummy word lines,for generating the reference potential in the second of each pair of bitlines; and a selection circuit for selecting either said first dummyword line driving circuit or said second dummy word line drivingcircuit, wherein each of said dummy word line driving circuitscomprises: a first MOS transistor connected between the first of thepair of dummy word lines and said precharging potential source, saidfirst MOS transistor being controlled by a precharge control signal; asecond MOS transistor connected between the second of the pair of dummyword lines and said precharging potential source, said second MOStransistor being controlled by a precharge control signal; a third MOStransistor connected between the pair of dummy word lines, said thirdMOS transistor being controlled by the precharge control signal; afourth MOS transistor Connected between the first of the pair of dummyword lines and said high-potential source, said fourth MOS transistorbeing controlled by an output of said selection circuit; a fifth MOStransistor connected between the second of said pair of dummy word linesand said low-potential source, said fifth MOS transistor beingcontrolled by an output of said selection circuit; a sixth MOStransistor connected between the first of said pair of dummy word linesand said precharging potential source, said sixth MOS transistor beingcontrolled by an output of said selection circuit; and a seventh MOStransistor connected between the second of said pair of dummy word linesand said precharging potential source, said seventh MOS transistor beingcontrolled by an output of said selection circuit.
 16. The dynamicmemory according to claim 15, wherein said first capacitors and saidsecond capacitors have the same capacitance.
 17. The dynamic memoryaccording to claim 15, wherein said selection circuit selects eithersaid first dummy word line driving circuit or said second dummy wordline driving circuit in accordance with an address signal used fordriving said word lines.